TAIPEI, TAIWAN—December 12, 2006— In collaboration with the University of Tokyo and Taiwan Semiconductor Manufacturing Company (TSMC), Alchip Technologies, a leading fabless ASIC company, today announced its first silicon success of the SING processor for GRAPE-DR, the next generation of the world’s fastest supercomputers targeting 2,000 trillion transactions per second (2PFLOPS). This chip features 512 CPUs on a single chip with over 60 million logic gates and 10 million bits of SRAM utilizing TSMC production-proven 90nm process and flip-chip package technology.

The GRAPE series are the world’s fastest supercomputers and six-time winner of the Gordon Bell Prize, an important recognition of outstanding achievement in high-performance computing. Its practical computation has yielded remarkable simulation results used worldwide for scientific research in exploring the planet and galaxy. GRAPE-DR is designed to compute over 31 times faster than its predecessor GRAPE-6 (64 trillion computations per second) and to cover general computing.

Development of the SING processor was highly challenging due to its large gate count complexity and performance target. The SING processor contains over 60 million logic gates aiming at 500MHz performance whole chip while consuming over 50 watts of power. Alchip was responsible for the complete design integration which includes physical, electrical, timing and thermal design of the System-on-Chip (SoC) project. The chip adopted TSMC’s 90nm eight-layer metal process with a silicon redistribution layer (RDL) in a flip-chip BGA package. Alchip’s divide-and-conquer methodology was used to partition the design into three levels of hierarchy for parallel implementation. Alchip’s unique on-chip clocking distribution structure achieved minimum global clock skew on the scale of 18mm by 18mm die size. It enabled high speed operation by avoiding serious nanometer on-chip variation (OCV) which can affect circuits performance. Closer collaboration with customer allowed Alchip to provide effective design and packaging solutions to achieve one-pass design tapeout and one-pass silicon success.

“Having selected Alchip as our SoC development partner, we are extremely delighted and satisfied with Alchip’s on-time & one-pass silicon success delivery of SING chip.” said Professor Kei Hiraki of the University of Tokyo. “Alchip demonstrated superior design and manufacturing capabilities and supported the development of GRAPE-DR project well. With Alchip’s efforts, we are able to test, demonstrate and bring GRAPE-DR to the market on time.”

“TSMC supports a broad range of existing and emerging applications,” said Makoto Onodera, president of TSMC Japan. “The GRAPE-DR project achieved the first silicon success and marks a major collaborative milestone among private, public, and academic segments.”

“Alchip is pleased to provide total SoC solutions to the University of Tokyo for the fastest supercomputer in the world,” said Kinying Kwan, chairman, president and chief executive officer of Alchip. “The first silicon success of this complex and challenging chip illustrates Alchip’s superior SoC design capabilities in cutting-edge technologies and demonstrates our robust turnkey infrastructure that seamlessly integrates physical design, IP, fabrication, packaging and testing solutions. We will continue to delight our customers by powering them with the fastest time-to-market and the lowest total cost of ownership.”

About GRAPE-DR

GRAPE-DR is a research project funded by the University of Tokyo, National Astronomical Observatory of Japan, Institute of Physical and Chemical Research, NTT Communications plus corporations and research organizations. Its goals are to construct a 2PFLOPS computing engine and global research infrastructure utilizing multi-10 Gbps networks by 2008.  For information about the GRAPE-DR project, visit http://grape-dr.adm.s.u-tokyo.ac.jp/index-en.html

or contact Professor Kei Hiraki at hiraki@is.s.u-tokyo.ac.jp

Contacts:

Alchip Technologies, Limited

jp_info@alchip.com

+81-45-470-1090

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The University of Tokyo

Professor Kei Hiraki

hiraki@is.s.u-tokyo.ac.jp