Alchip Ups Backend Engineering Investments to Meet Heightened Demand

Packaging Capabilities Become Critical High-Performance ASIC Differentiation


Taipei, Taiwan December 14, 2021–Recent demands for more sophisticated backend high-performance ASIC differentiation through packaging and test implementation has moved Alchip Technologies, Ltd. to focus investment in engineering resources that emphasize this innovation-critical capability. The company has consolidated advanced packing engineering services to more efficiently integrates these capabilities into the manufacturing value chain.

The increased focus accommodates an emerging trend for hyperscalers and OEMs to rely heavily on front-end IC design, amassing large teams of chip design engineers to create highly customized silicon. They’re then partnering with high-performance ASIC companies who can provide reticle-size FinFET expertise to create additional differentiation through backend performance differentiation.

One result of this trend is the emergence of several different customer engagement points. Engagement is now determined by the proportion of chip IP and overall design that is customer-implemented versus that which ASIC partner implemented.

With continuing customer focus on front end design, Alchip is answering increased market demand by focusing on advanced packaging and product manufacturing as distinct value chain resources.

Over the past nine months, the company has seen an exponential increase in these post-GDSII assignments across all high-performance computing ASIC applications. The company’s most recent activity has driven a track record of over 470 backend tape outs and billions of devices now coming out of production.

“The hyperscalers today are investing heavily in upfront design to create differentiation. As a result, they’re looking for ASIC companies who can provide the backend capabilities to maximize their investment in differentiated front end design with equally innovative backend differentiation. These once-pedestrian practices are now highly prized for wringing out every last bit of performance power and area,” observes Johnny Shen, Alchip Technologies’ President & CEO.

Backend Keys Last Mile Success

Alchip’s post-GDSII services are experiencing high demand as system OEMs and hyperscalers face both technology challenges and engineering talent limitations associated with traditional backend services.

Sophisticated high-performance frontend design resources are expensive and, depending on geographic location, somewhat scarce. The result is an uptick in companies outsourcing packaging, testing, and production responsibilities to ASIC companies who are far more experienced in these strategic areas.

Alchip has elevated its advanced package engineering (APE) capabilities to include Chip-on-Wafer-on-Substrate (CoWoS®) and InFO, first developed by TSMC. Alchip’s CoWoS process runs on dedicated tooling and demonstrates IP performance equivalent to that of an original design. The process also includes online debugging and active thermal control. The company’s in-house substrate design and test capabilities assure compliance with all system requirements and establishes the frame work for critical foundry-to-final test flow.

To secure the requisite quality for complete physical designs, the company implements a two sign-off verification options to accommodate both design economics and enhanced yield objectives. Standard sign-off verification option includes DRC/LVS/ERC checks that guard against fatal manufacturing error. A second design options calls for additional focus on Electrical, DFT, STA and/or clock verification, depending on specific customer requirements.

“Our key to success is knowing how to target advanced technology so that we can collaborate with the customers to develop a manufacturing protocol that is done ‘their way’ rather than one monolithic approach that is done our way,” explains Mr. Shen.

Alchip’s has aligned the backend of its high-performance computing ASIC services to tackle the increased for production, packaging, test and assembly that has emerged with transition to 5nm and below advanced technology nodes.